FPU

I expanded my SystemVerilog experience by expanding an in-class project. During my first foray into FPGA programming, we had built a simple, non-floating point CPU to learn about the timing and how to set up the operations. For our FPGA project, I decided to expand the CPU into more of a full processor by adding an IEEE 754 compliant Floating Point Unit (FPU). This project was solo, with all research and implementation done by me, with advice given by my professors.

FPU Operations:

  • General Ops

    • AND/NAND

    • OR/NOR/XOR

    • LDR/STR/MOV

    • LSL/LSR

    • BR/BEQ/BNE

    • NOP

    • DtoF/FtoD

  • Integer Ops

    • Add/Sub

    • Mul/Div

  • Float Ops

    • AddF/SubF

    • MulF/DivF

    • SQRT

The Floating Point Unit project was a fun one to take on. It was my first time really digging into SystemVerilog to find out what I could do with it. I had to research what makes up the IEEE 754 standards, then cutting it down to what I could accomplish in 4 weeks. The goal was to make it as compliant to the standard as possible.

To start with, I added in all the basic float operations. I wanted to make sure it could add and subtract, multiply and divide. The division was by far the hardest part of this process. I had to make sure the division process could work fast enough to match up with the rest of the CPU, but of course also be correct. This made me do a ton of research into SystemVerilog and VHDL optimization methods. In the end, it all came together.
 

Later on I plan to implement the other IEEE compliance features on my own. The project period was unfortunately short, and I took a complex project to challenge myself. The smaller complaint features like rounding are something to be added later. Time permitting, I should be able to combine this with my existing CPU and have a full desktop processor!

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